Cisco MDS 9396V 64G 2RU FC Switch

Overview

Highlights

• High performance: MDS 9396V architecture, with centralized nonblocking arbitration, provides consistent 64-Gbps low-latency performance across all traffic conditions for every Fibre Channel port on the switch.
• Fully integrated SAN Analytics: This feature-rich switch also offers state-of-the-art data traffic analytics and telemetry capabilities that have been built into this next-generation hardware platform. This switch has a hardware Analytics Engine that can compute I/O metrics at line rate on all port.
• Telemetry: Fibre Channel and Small Computer System Interface (SCSI) or NVMe headers can be inspected without the need for any external taps or appliances. The resulting metrics can be analyzed on the switch and can additionally be exported in an industry-leading open telemetry format using the mgmt port for telemetry and analytics purposes.
• Cisco Dynamic Ingress Rate Limiting (DIRL): MDS 9396V supports the Dynamic Ingress Rate Limiting feature. Using DIRL, the MDS SAN can automatically detect any symptoms of congestion and then dynamically rate limit the congested and slow-drain devices so that adverse effects are not spread to other devices across the SAN. DIRL dynamically adapts the rate-limiting to suit the traffic pattern of the congestion or slow-drain device.
• Capital Expenditures (CapEx) savings: The 64-Gbps ports allow users to deploy them with existing 32- or 16-Gbps transceivers, thus providing investment protection, with an option to upgrade to 64-Gbps transceivers and adapters whenever needed.
• High availability: the MDS 9396V switch is designed to provide 99.999 percent availability. It provides such outstanding availability and reliability by having redundancy on all major components, such as the power supply and cooling subsystems. Dual power supplies also facilitate redundant power grids. In addition, port-channel link members can be striped across four 24-port port groups, thus providing additional high availability.
• Reliability: As part of the standard 64-Gbps Fibre Channel specification, Cisco provides FEC on all 64-Gbps Fibre Channel fixed switches. This feature helps ensure bit errors up to a certain threshold introduced in flight get corrected at the receive side of the link. In addition, Cisco extends Buffer-to-Buffer Credit Recovery through Buffer-to-Buffer State Change Notification (BBSCN) to all port types that are attached to any end device. Over time, the corruption of receiver-ready, known as R_RDY primitives, can lead to a loss of credits, which can eventually cause a link to stop transmitting in one direction. Buffer-to-Buffer credit recovery provides for two attached ports to detect and correct this situation without impact to traffic flow.
• Next-generation ASIC: The MDS 9396V Fibre Channel switch is powered by Cisco developed next- generation high-performance 64-Gbps ASICs.
• Government Purchase Card (GPC) accepted